Digital filter for reducting blocking artifacts in images

ABSTRACT

The present invention relates to a digital data filtering circuit. This digital data filtering circuit is able to implement the calculation steps of a discrete transform of a set of 8 original data (w), and calculating an inverse discrete transform of the set of transformed data thus obtained. For this purpose, it comprises a first filtering module (FILo 1 ) intended to filter the odd transformed data or the 3 odd transformed data items having the highest frequencies in the set of transformed data, and a second filtering module (FILo 2 ) connected to the first filtering module and intended to filter the 2 odd transformed data having the highest frequencies in the set of transformed data.

The present invention relates to a digital data filtering device able toimplement the steps of calculating a discrete transform of a set of 8original data, and calculating an inverse discrete transform of the setof transformed data thus obtained, said circuit being able to filter atleast one data item among the set of transformed data.

It finds in particular its application in video decoders, in portableapparatus including such decoders and in television receivers. In thesedevices, the correction of digital images previously coded and thendecoded according to a block-based coding technique, the MPEG (“MovingPictures Expert Group”) standard for example, is necessary forattenuating the visual artifacts caused by said block-based codingtechnique.

The video compression algorithms using block-based coding techniquessometimes result in a degradation of the quality of the coded and thendecoded images. One of the visual artifacts most often observed withthese coding techniques is called the blocking artifact.

The article entitle “A projection-based post-processing technique toreduce blocking artifacts using a priori information on DCT coefficientsof adjacent blocks”, published by Hoon Paek and Sang-Uk Lee, in“Proceedings of 3^(rd) IEEE International Conference on ImageProcessing, Vol. 2, Lausanne, Switzerland, 16-19 Sep. 1996, p. 53-56”describes a method of filtering data contained in a digital image. Thepurpose of this data filtering method is to correct, in the frequencydomain, the coefficients which correspond to these blocking artifacts.

It is based on the following principle. Let there be two adjacentsegments u and v, as illustrated in FIG. 1, belonging respectively totwo blocks Bu and Bv of pixels and disposed on each side of a block edgeEDG. If a blocking artifact is present between the segments u and v, thesegment w corresponding to the concatenation of the first and secondsegments includes spatial high frequencies which go beyond those of thesegments u and v.

In order to find and eliminate the frequencies associated with theblocking artifacts, the data filtering method of the state of the art,illustrated in FIG. 2, comprises the following steps of:

-   -   calculating a discrete cosine transformation DCTN (21) of the        segment u of N pixels with N=8 in the following example:

$\begin{matrix}{{U = {{{DCTN}\lbrack u\rbrack} = \left\{ {{U(0)},{U(1)},\ldots\mspace{11mu},{U\left( {N - 1} \right)}} \right\}}},{with}} \\{{U(k)} = {{\alpha(k)}\mspace{11mu}{\sum\limits_{n = 0}^{N - 1}{{u(n)}\;{\cos\left( \frac{{\pi\left( {{2n} + 1} \right)}k}{2N} \right)}}}}}\end{matrix}$where k is the frequency of the transformed data U, k ∈ [0,N=1];

-   -   calculating a discrete cosine transformation DCTN (22) of the        segment v adjacent to the segment u: V=DCTN(v)={V(0), V(1), . .        . , V(N−1)}, that is to say

${{V(k)} = {{\alpha(k)}\mspace{11mu}{\sum\limits_{n = 0}^{N - 1}{{v(n)}\;{\cos\left( \frac{{\pi\left( {{2n} + 1} \right)}k}{2N} \right)}}}}};$

-   -   calculating a discrete cosine transformation DCT2N (23) of the        segment w of 2N, that is to say 16 pixels, corresponding to the        concatenation CON (20) of the segments u and v: W=DCT(w)={W(0),        W(1), . . . , W(2N−1)}, that is to say

${{W(k)} = {\frac{1}{\sqrt{2}}{\alpha(k)}\mspace{11mu}{\sum\limits_{n = 0}^{{2N} - 1}{{v(n)}\;{\cos\left( \frac{{\pi\left( {{2n} + 1} \right)}k}{4N} \right)}}}}};$

-   -   calculating PRED (24) a predicted maximum frequency kwpred        according to the maximum frequencies kumax and kvmax of U and V,        as follows:        -   kwpred=2.max(kumax, kvmax)+2        -   with kumax=max (k∈{0, . . . ,N−1}/U(k)≠0),            -   kvmax=max (k∈{0, . . . ,N−1}/V(k)≠0), and            -   max is the function which gives the maximum of k from                among a set of given values;    -   correcting by zeroing ZER (25) the odd transformed data W        resulting from the global discrete transform whose frequency is        higher than the predicted maximum frequency, supplying corrected        transformed data Wc;    -   calculating an inverse discrete cosine transformation IDCT2N        (26) of the corrected transformed data, supplying filtered data        wf which are then intended to be displayed on a screen.

The aim of the present invention is to propose a data filtering circuitfor implementing simply the data filtering method of the state of theart.

This is because the implementation of such a method may prove to becomplex in terms of number of operations, in particular with regard tothe sequence comprising the discrete cosine transformation DCT2N,followed by the correction of the odd transformed data and the inversediscrete cosine transformation IDCT2N. FIG. 3 illustrates what would bea conventional implementation of such a sequence in the case where 2N=8.The direct DCT2N and inverse IDCT2N discrete cosine transformationsprocess the 2N concatenated data w(0) to w(7) using the Lee algorithm.The black circles represent additions, a horizontal dotted linepreceding a black circle corresponding to a data item to be subtracted.The white circles correspond to multiplications. The multiplications anddivisions by a power of 2 have not been depicted in the diagram in FIG.3 and the following figures since they have little influence on thecomplexity of the implementation.

The implementation of the global discrete cosine transformation DCT2Ncomprises four successive stages separated in FIG. 3 by vertical dottedlines, namely:

-   -   a first stage ST1 comprising 8 adders performing additions or        subtractions using the concatenated data w(0) to w(7),    -   a second stage ST2 comprising 4 adders and 2 data rotation units        C1 and C3, a rotation unit comprising 2 adders and 4 multipliers        according to a principle known to a person skilled in the art,    -   a third stage ST3 comprising 6 adders and one rotation unit        √2C1, and    -   a fourth stage ST4 comprising 2 adders and 2 multipliers, and        supplying the odd transformed data W(1), W(3), W(5) and W(7),        the even transformed data W(0), W(2), W(4) and W(6) resulting        from the data processed by the third stage and not processed in        the fourth stage.

The implementation of the correction by zeroing of the odd transformeddata resulting from the discrete transform DCT2N whose frequency isgreater than the predicted maximum frequency, not shown in FIG. 3, iseffected by means of logic circuits implementing the function “AND”between a transformed data item W(i) and an output of a control circuitable to deliver a “1” level or a “0” level according to the value of thepredicted maximum frequency.

The implementation of the inverse discrete cosine transformation IDCT2Ncomprises 4 successive stages:

-   -   a fifth stage ST5 comprising 2 adders and 2 multipliers able to        process the corrected odd transformed data,    -   a sixth stage ST6 comprising 6 adders and one rotation unit        √2C1,    -   a seventh stage ST7 comprising 4 adders and 2 rotation units C1        and C3, and    -   an eighth and last stage ST8 comprising 8 adders, and supplying        the filtered data wf(0) to wf(7).

The circuit for filtering data resulting from this conventionalimplementation would therefore lead to a complex solution comprising twotransformations DCTN, a transformation DCT2N and a transformationIDCT2N, requiring a total of 36 multiplications and 68 additions.

In order to remedy this drawback, the filtering circuit according to theinvention is characterized in that it comprises:

-   -   a first filtering module intended to filter the 3 odd        transformed data having the highest frequencies in the set of        transformed data,    -   a second filtering module connected to the first filtering        module and intended to filter the 2 odd transformed data having        the highest frequencies in the set of transformed data.

With a data filtering circuit having a modular structure of this type,the number of multipliers and adders is reduced since it has beenpossible to optimize each module by taking account of its destination,as will be seen in more detail later in the description. Theimplementation of the data processing sequence comprising the twotransformations DCTN and then in series the transformation DCT2N, thecorrection of the transformed data and the inverse transformation IDCT2Nare thus simplified. In addition, the modular structure of the filteringcircuit makes it possible to deactivate the modules which are notoperational in the circuit at a given moment and to have an optimizedstructure in the part which is activated, resulting in a filteringcircuit which is both less expensive and has lower power consumption.

The invention will be further described with reference to examples ofembodiments shown in the drawings to which, however, the invention isnot restricted.

FIG. 1 illustrates two adjacent segments disposed on each side of ablock edge,

FIG. 2 shows the data processing method of the state of the art,

FIG. 3 illustrates a circuit implementing in a conventional manner thedata processing method of the state of the art,

FIG. 4 a and FIG. 4 b depict two sets of pixels which can be processedby the filtering circuit according to the invention,

FIG. 5 a illustrates a conventional implementation of a rotation whilstFIG. 5 b illustrates a simplified implementation of said rotationaccording to the invention,

FIG. 6 is a diagram depicting a first filter intended to filter oddtransformed data,

FIG. 7 a diagram depicting a second filter intended to filter oddtransformed data,

FIG. 8 is a diagram depicting a third filter intended to filter oddtransformed data,

FIG. 9 depicts schematically a circuit intended to implement a DCTNtransformation,

FIG. 10 is a diagram depicting a fourth filter intended to filter eventransformed data,

FIG. 11 depicts schematically the filtering circuit according to theinvention.

The present invention relates to a digital data filtering circuit makingit possible to correct blocking artifacts in the frequency domain.

In the following description, the discrete transform is a discretecosine transformation DCT or IDCT. It will be clear however to a personskilled in the art that the present invention applies to any lineardiscrete transform.

In the example described below for data coded and then decoded accordingto the MPEG standard, the sets of data u and v each contain theluminance values associated with N=4 consecutive pixels.

In the case of the MPEG standard, the processing sequence comprising theDCTN, DCT2N and IDCT2N transformations is applied to a set of 16 data,the method used being referred to as DFD-16 and providing an excellentimage quality at the output. In order to save on calculation resources,it is more advantageous to apply the processing sequence to a set of 8data according to the principle in FIG. 4 a, with segments u and v of 4consecutive pixels distributed immediately on each side of a block edge.This solution, known as DFD-8, has the merit of reducing the complexityof the filtering method to the detriment however of its efficiency andtherefore the quality of the image obtained at the output of thefiltering.

This is why, in the preferred embodiment, the sets of data u and v arerespectively subdivided into two subsets u′, u″ on the one hand and v′,v″ on the other hand, the subsets u′, v′ containing the data of odd rankand the subsets u″ and v″ containing the data of even rank. The sets u′,v′ and w′ are depicted in FIG. 4 b.

The calculation steps of the DCTN and DCT2N transformations are appliedto the subsets u′, v′ on the one hand and u″, v″ on the other handsupplying respectively the transformed data U′, V′, W′ on the one handand U″, V″, W″ on the other hand.

The determination step PRED supplies in parallel the predicted maximumfrequencies kw′pred and kw″pred calculated as follows:

-   -   kw′pred=2.max(ku′max, kv′max)+2    -   with ku′max=max(k∈{0, . . . ,N−1}/abs(U′(k))>Th or Tv)        -   kv′max=max(k∈{0, . . . ,N−1}/abs(V′(k))>Th or Tv)    -   kw″pred=2.max(ku″max, kv″max)+2    -   with ku″max=max(k∈{0, . . . ,N−1}/abs(U″(k))>Th or Tv)        -   kv″max=max(k∈{0, . . . ,N−1}/abs(V″(k))>Th or Tv)

where, for example, Th=10 and Tv=5 in the case of a frame comprising twointerlaced fields in the standard format (one field comprises 228 linesof 720 pixels).

The correction step ZER is then applied independently to the transformeddata W′ and W″ with:

-   -   a substep of detecting natural contours such that, for example:    -   |ū′− v ′|>25, ku′max<1 and kv′max<1    -   or |ū″− v ″|>25, ku″max<1 and kv″max<1    -   a substep of zeroing the transformed data W′ or W″ resulting        from the global discrete transform whose frequency is higher        than the predicted maximum frequency kw′pred or kw″pred.

This embodiment, called DFD-8eo, makes it possible to have a complexityequal to the DFD-8 method in terms of number of gates but with doublefrequency, whilst preserving a good image quality at the output of thefiltering.

Finally, in the case of data coded and then decoded according to theH.264 standard, the filtering method is applied directly to datasegments u and v which each contain the luminance values associated withN=4 consecutive pixels, the coding blocks according to this standardbeing 4×4 pixels.

When implementing the data filtering method described above in thepresent invention, certain simplifications are made.

A first simplification can be made with regard to the implementation ofthe rotations. If X0 and X1 are the inputs of a rotation and Y0 and Y1the outputs, these variables are linked by the following equations:Y0=a*X0+b*X1Y1=−b*X0+a*X1

FIG. 5 a illustrates a conventional implementation of the rotation whichthen comprises 4 multiplications and 2 additions. The precedingequations can be rewritten in the following form:Y0=(b−a)*X1+a*(X0+X1)=A*X1+a*(X0+X1)Y1=−(a+b)*X0+a*(X0+X1)=B*X0+a*(X0+X1)

FIG. 5 b illustrates the new implementation of the rotation, which thencomprises no more than 3 multiplications and 3 additions, onemultiplication having been replaced by an addition, which reduces thecomplexity of the processing circuit, an adder having a simplerstructure than a multiplier.

A second simplification consists of calculating the odd transformed dataW(k) resulting from the DCT2N transformation directly from thetransformed data U(k/2) and V(k/2) resulting from the DCTNtransformation according to the following equation:

${{W(k)} = {{\frac{1}{\sqrt{2}}\left( {{U\left( \frac{k}{2} \right)} + {\left( {- 1} \right)\;\frac{k}{2}{V\left( \frac{k}{2} \right)}}} \right)\mspace{14mu}{with}\mspace{14mu} k} = 0}},2,4,6.$

FIG. 6 depicts a first filter FILo1 intended to filter the oddtransformed data W(3), W(5) and W(7). A conventional implementation asdepicted on the left of FIG. 6 consists of eliminating the wirescorresponding to the zeroed transformed data. As a conventional rotationcomprises 2 additions and 4 multiplications, the conventionalimplementation consists of 11 additions and 16 multiplications.

However, if Q and S are the inputs of a rotation C1 or C3 situated onthe same side as the DCT2N transformation and followed by an adder, thisgives:(a*Q+b*S)+(−b*Q+a*S)=Q(a−b)+S(a+b),

a and b being multiplying coefficients easily determined by a personskilled in the art according to the type of discrete transform used. Theinvention therefore proposes, in this case, to replace a rotation withtwo multipliers whose respective multiplying coefficients are (a−b) and(a+b).

In addition, the inputs of a rotation C1 or C3 situated on the same sideas the inverse transformation IDCT2N are identical and equal to W(1).The outputs of a rotation are then:W(1)(c−d) and W(1)(c+d)

c and d being multiplying coefficients easily determined by a personskilled in the art according to the type of discrete transform used. Theinvention therefore proposes in this case to replace a rotation with twomultipliers with the respective multiplying coefficients (c−d) and(c+d). Consequently, each rotation having been replaced by twomultipliers as depicted on the right in FIG. 6, the implementation ofthis first filter therefore comprises no more than 3 adders and 8multipliers.

FIG. 7 depicts a second filter intended to filter the transformed dataW(5) and W(7). A conventional implementation, as depicted on the left inFIG. 7, consists of eliminating the wires corresponding to the zeroedtransformed data. As a conventional rotation comprises 2 additions and 4multiplications, the conventional implementation consists of 14additions and 18 multiplications.

The 2 multiplications by √2 can be omitted, one multiplication out of 2amounting to a shift which is easy to implement. The transformed dataitem is then no longer W(3) but Wm(3), equal to W(3)/√2 before shiftingand √2W(3) afterwards.

Using the linear properties of the multiplication, it is possible todecompose the filter according to the contribution of W(1) and that ofWm(3). It is then possible to draw on the modifications made for thefilter FILo1 in order to simplify the structure around Wm(3) and resultin the representation appearing on the right in FIG. 7 comprising, likethe filter FILo1, 3 adders and 8 multipliers, the outputs of the last 4multipliers then being added to the outputs of the filter FILo1. Thepart of the second filter external to the filter FILo1 is called filterFILo2. The final structure of the second filter, although comprisingonly 10 adders and 16 multipliers, that is to say less than theconventional implementation, is not optimal. However, it has the meritof reusing the filter FILo1, which means that the contribution of thenew filter in terms of operators is in fact only 7 adders and 8multipliers.

FIG. 8 depicts a third filter intended to filter only the coefficientW(7). It takes advantage of the linearity of the direct DCT and inverseIDCT discrete cosine transformations. For this purpose, the transformeddata W can be divided into 2 subsets:

-   -   a first subset WZ corresponding to the frequencies for which the        transformed data must be zeroed;    -   a second subset WNZ corresponding to the frequencies for which        the transformed data must not be zeroed.

The transformed data W thus correspond to the concatenation of these twosubsets, that is to say:W=WZ|WNZ.

The filtered data wf are obtained by applying an inverse discrete cosinetransformation to the corrected transformed data, which are either equalto WNZ or equal to 0, or in other words:wf=IDCT(WNZ|0).

Using the linearity of the inverse discrete cosine transformation, thereis obtained:wf=IDCT(WNZ|WZ)−IDCT(0|WZ),

that is to say again wf=w−IDCT(0|WZ).

Giving the term Dw to the differential data which correspond to thedifference between the original data w and the filtered data wf, meansthat:Dw=IDCT(0|WZ) and wf=w−Dw.

In this way a filter is obtained which functions in differential modeand a particularly economical implementation of which is illustrated inFIG. 8. The data filtering circuit according to this operating modecomprises:

-   -   a stage comprising 4 adders each performing, for lines 4 to 7, a        subtraction of an original data item w(j) of line j from an        original data item w(7−j) of line (7−j), and delivering odd        intermediate transformed data;    -   the circuit FILo1 previously described;    -   a stage comprising 8 adders each performing:        -   for lines j=0 to 3, a subtraction of an intermediate            filtered data item of line (7−j) issuing from the circuit            FILo1 from the original data item w(j) of line j,        -   for lines j=4 to 7, an addition of an intermediate filtered            data item of line j issuing from the circuit FILo1 and the            original data item w(j) of the same line.

The structure of the third filter because of this reuses the filterFILo1, which means that its contribution in terms of operators is zero.

FIG. 9 depicts the circuit implementing a DCTN transformation, that isto say here a DCT4. Such a transformation comprises 6 additions and onerotation, that is to say finally 9 additions and 3 multiplications. Thistransformation is performed twice, once for the data segment u and oncefor the data segment v, requiring in total 18 additions and 6multiplications.

In a particularly advantageous embodiment, it is possible also to filterthe odd transformed data. This is particularly the case when thequantization step is greater than a predetermined value Qth, for exampleequal to 10 in the case of an implementation according to the MPEG-4standard. This predetermined value corresponds to a threshold beyondwhich the image quality is greatly impaired, a correction to eventransformed data mitigating this impairing. FIG. 10 depicts the filterFILe able to filter the transformed data item W(6) and where necessarythe transformed data item W(4). The even transformed data W(i) arededuced from the transformed data U(i) and V(i) as follows:W(0)=1/√{square root over (2)}(U(0)+V(0))W(2)=1/√{square root over (2)}(U(1)−V(1))W(4)=1/√{square root over (2)}(U(2)+V(2))

If the transformed data item W(4) is to be filtered, a multiplexerreplaces its value with zero. After simplification, the fourth filtertherefore comprises 9 adders and 2 multipliers, the eighth stage ST8 nothaving been taken into account.

FIG. 11 depicts the filtering circuit according to the invention. Thecircuit comprises a transformation module DCT4 comprising two circuitsaccording to FIG. 9 or only one operating a double frequency andintended to calculate the discrete transform of the data segments u andv. It comprises a control circuit CTRL intended to calculate thecoefficient kwpred from transformed data u and v and to determine thefiltering module or modules to be used from kwpred and the quantizationstep Q. According to the values of kwpred and Q, the transformed datafrequencies W which are to be filtered by the even filter FILe or theodd filter FILo are given in the following table:

Q < 10 Q > 10 kwpred FILe FILo FILe FILo 2 — 3, 5, 7 4, 6 3, 5, 7 4 — 5,7 6 5, 7 6 — 7 — 7 8 — — — —

The filtering circuit according to the invention comprises two modules4ADD and 4 adders each intended to form the additions of the originaldata w(0) to w(7) in accordance with the first stage ST1 of FIG. 3. Italso comprises registers REG able to store on the one hand the resultsof the first adding module corresponding to the 4 higher additions ofthe first stage ST1 of FIG. 3 and on the other hand the original dataw(0), w(1), w(2) and w(3). The filtering circuit comprises a firstfiltering module FILo1 intended to filter the last odd transformed dataitem W(7) or the last 3 odd transformed data W(3), W(5) and W(7), and asecond filtering module (FILo2) intended to filter the last 2 oddtransformed data W(5) and W(7). These filtering modules receive as aninput the outputs of the second adding module corresponding to the 4lower additions of the first stage ST1 of FIG. 3 and each deliver 4intermediate filtered data, the second filtering module FILo2 using theoutputs of the first filtering module FILo1. Finally, the filteringcircuit comprises a third filtering module FILe intended to filter thelast even transformed data item W(6) or the last 2 even transformed dataW(4) and W(6) from the 6 transformed data U(0), V(0), U(1), V(1), U(2),V(2).

The control circuit CTRL then controls two multiplexers MUX, the firstmultiplexer making it possible to choose between the 4 outputs of thefilter FILe and the data stored in the registers REG equal either to the4 outputs of the first adder module or to the original data w(0), w(1),w(2) and w(3). The second multiplexer makes it possible to choosebetween the outputs of the filtering module FILo1 and those of thefiltering module FILo2. The outputs of the two multiplexers are thensent to the input of a module 8ADD of the 8 adders intended to performthe additions in accordance with the eighth stage ST8 of FIG. 3 or ofFIG. 8 in the case of the filtering of the transformed data item W(7)alone, resulting in filtered data wf(0) to wf(7).

If the value of kwpred is such that no filtering is necessary, theoutput of the filtering circuit consists of the original data w(0) tow(7), the control circuit CTRL controlling, for example, a multiplexer,not shown in the diagram, making it possible to choose between thefiltered data wf and the original data w.

The complexity of said method is given in the following table for thevarious possible filtering configurations and for the conventionalimplementation of the filtering method:

Configuration Filtered data Additions Multiplications Conventional 76 32Filtering step — 18 6 A 7 33 14 B 5, 7 44 22 C 3, 5, 7 37 14 D 5, 6, 749 24 E 3, 4, 5, 6, 7 42 16

The filtering circuit according to the invention performs a maximum of49 additions and 24 multiplications, and hence there is an appreciablereduction in complexity compared with a conventional implementation. Thefiltering circuit can also be adapted to the content of the imagerepresented by the coefficients kwpred and Q, which makes it possible toreduce the number of adders and multipliers used according to the typeof filtering determined by the control circuit CTRL. The reduction inthe number of operations performed by the filtering circuit thus makesit possible to save on the calculation resources or to accelerate thetime taken to process the original data.

A first application of the invention consists of a video decoder able tosupply decoded digital images and comprising a filtering circuitaccording to the invention, able to filter the decoded digital image soas to supply filtered digital images. This video decoder can beintegrated in a portable apparatus in order to display the filtereddigital data on a screen of said apparatus. This portable apparatus is,for example a mobile telephone or a personal digital assistantcomprising an MPEG-4 video decoder.

Another application of the invention consists of a television receivercomprising a filtering circuit according to the invention, able tofilter the digital images received by said receiver so as to displayfiltered digital images on a screen of said receiver.

The present invention has been described in the case of a filteringdevice able to filter a set of 8 digital data. A similar principle,based on a modular structure using the simplifications described above,can be applied to digital data filtering devices able to implement thecalculation steps of a linear discrete transform of a set of 2^(p)original data, p being an integer greater than 3, and calculating alinear inverse discrete transform of the set of transformed data thusobtained.

No reference sign between parentheses in the present text should beinterpreted limitingly. The verb “comprise” and its conjugations doesnot exclude the presence of elements or steps other than those listed ina sentence. The word “a” or “one” preceding an element or a step doesnot exclude the presence of a plurality of these elements or steps.

1. A digital data filtering circuit to correct blocking artifacts in afrequency domain within a block-based video processing device, thedigital data filtering circuit comprising: means for performing adiscrete linear transform to transform a set of input luminance values,from two adjacent video segments, into a corresponding set oftransformed values in the frequency domain, wherein the transformedvalues in the frequency domain comprise a plurality of even transformeddata values and a plurality of odd transformed data values; means forperforming an inverse discrete linear transform to transform thetransformed values from the frequency domain to a corresponding set offiltered values for use on a display device coupled to the videoprocessing device; and a control circuit coupled to the means forperforming the discrete linear transform and the inverse discrete lineartransform, wherein the control circuit is configured to selectivelyactivate at least one of a plurality of filtering modules, wherein theplurality of filtering modules comprises at least one odd filteringmodule to filter at least one of the odd transformed data values and atleast one even filtering module to filter at least one of the eventransformed data values.
 2. The digital data filtering circuit of claim1, wherein the control circuit is further configured to selectivelyactivate the at least one of the plurality of filtering modules based ona predicted maximum frequency (kwpred) and a quantization step (Q). 3.The digital data filtering circuit of claim 1, wherein the means forperforming the discrete linear transform and the inverse discrete lineartransform comprise: a first odd filtering module (FILo1) of theplurality of filtering modules, wherein the first odd filtering moduleis configured to filter three of the odd transformed data values,wherein the three odd transformed data values filtered by the first oddfiltering module comprises: a first odd transformed data value having ahighest frequency out of the odd transformed data values; a second oddtransformed data value having a second highest frequency out of the oddtransformed data values; and a third odd transformed data value having athird highest frequency out of the odd transformed data values; and asecond odd filtering module (FILo2) of the plurality of filteringmodules, the second odd filtering module coupled to the first filteringodd module, wherein the second odd filtering module is configured tofilter the first and second odd transformed data values having thehighest and second highest frequencies, respectively.
 4. The digitaldata filtering circuit of claim 3, wherein the means for performing thediscrete linear transform and the inverse discrete linear transformfurther comprise: discrete transform means coupled to the controlcircuit, the discrete transform means to transform a first half of theset of input luminance values into a first half of the transformedvalues in the frequency domain, and to transform a second half of theset of input luminance values into a second half of the transformedvalues in the frequency domain; and an even filtering module (FILe)coupled to the control circuit, wherein the even filtering module isconfigured to filter at least one of the even transformed data values,wherein the at least one even transformed data value filtered by theeven filtering module comprises a first even transformed data valuehaving a highest frequency out of the even transformed data values. 5.The digital data filtering circuit of claim 4, wherein the evenfiltering module is further configured to filter the first eventransformed data value and a second even transformed data value, whereinthe second even transformed data value comprises a second eventransformed data value having a second highest frequency out of the eventransformed data values.
 6. The digital data filtering circuit of claim4, wherein the discrete transform means is further configured totransform the first and second halves of the set of input luminancevalues into the first and second halves of the transformed values in thefrequency domain, respectively, in succession at a double frequency. 7.The digital data filtering circuit of claim 4, wherein the first half ofthe set of input luminance values comprises data of even parity from oneof the two adjacent video segments, and the second half of the set ofinput luminance values comprises data of even parity from the other ofthe two adjacent video segments.
 8. The digital data filtering circuitof claim 4, wherein the first half of the set of input luminance valuescomprises data of odd parity from one of the two adjacent videosegments, and the second half of the set of input luminance valuescomprises data of odd parity from the other of the two adjacent videosegments.
 9. The digital data filtering circuit of claim 4, wherein thefirst half of the set of input luminance values comprises highest rankdata one of the two adjacent video segments, and the second half of theset of input luminance values comprises lowest rank data from the otherof the two adjacent video segments.
 10. A video decoder comprising thedigital data filtering circuit of claim 1, wherein the video decoder isconfigured to supply filter digital images and supply decoded digitalimages to the display device.
 11. A portable apparatus comprising thedigital data filtering circuit of claim 1 and the display device,wherein the portable apparatus is configured to display filtered digitalimages on the display device.
 12. A television receiver comprising thedigital data filtering circuit of claim 1, wherein the televisionreceiver is configured to filter digital images received by thetelevision receiver and to display filtered digital images on a screencoupled to the television receiver.